1. Field of the Invention
The present invention relates to an embedded inductor, and more particularly, to an embedded inductor that can be applied in a wiring board or a chip package.
2. Description of the Related Art
In general, the conventional wiring board for carrying and electrically connecting a plurality of electronic elements is mainly composed of a plurality of patterned conductive layers and a plurality of insulating layers. The patterned conductive layers and the insulating layers are deposited interleavedly. The patterned conductive layers are formed by performing a patterning process on the copper foil defined by photolithography and etching, and the insulating layers are respectively disposed between any two adjacent patterned conductive layers for isolating these patterned conductive layers. In addition, the interleaved patterned conductive layers are electrically connected with each other through the conductive vias passing through the insulating layers. Moreover, various electronic elements (such as active elements or passive elements) may be further disposed on the surface of the wiring board, and the electrical signal is propagated through the internal circuit of the wiring board.
The passive elements mentioned above may be a capacitor, a resistor, or an inductor, and such passive elements may be disposed on the surface of the wiring board by the SMT (Surface Mounting Technology). In addition, the passive elements may be embedded inside the wiring board to increase the layout space on the surface of the wiring board. Please refer to FIGS. 1A and 1B for the structure of the embedded inductor element. FIG. 1A is a perspective view of a conventional embedded inductor suitable for a wiring board, and FIG. 1B is a top view of the conventional embedded inductor suitable for the wiring board. The conventional embedded inductor 100 is suitable for a wiring board 10. The wiring board 10 comprises four patterned conductive layers 12, three insulating layers, and a plurality of conductive vias 16. A conductive spiral structure 110 comprising a plurality of conductive traces 112a, a plurality of row conductive traces 112b, and a plurality of conductive vias 16 is formed in a spiral pattern. The conductive traces 112a are formed of the top patterned conductive layer 12a, and the conductive traces 112a are substantially parallel to each other. Similarly, the conductive traces 112b are disposed below the bottom patterned conductive layer 12b, and the conductive traces 112b are substantially parallel to each other. Referring to FIG. 1B, the left terminals of the conductive traces 112a and 112b are defined as the first terminals, and the right terminals of the conductive traces 112a and 112b are defined as the second terminals. In addition, a second terminal of one of the conductive traces 112a is electrically coupled to a second terminal of the conductive trace 112b through the conductive via 16. The first terminal of the same conductive trace 112b is electrically connected to the first terminal of another adjacent conductive trace 112a through another conductive via 16. By repeating such structure, a solenoid inductor is formed.
However, the conventional embedded inductor occupies a large space in the wiring board. In addition, a parasitic capacitance effect occurs when the conventional embedded inductor is cooperated with other patterned conductive layers. Thus, the self-resonance frequency of the embedded inductor is decreased, and the quality factor Q of the embedded inductor is also reduced. Accordingly, how to reduce the parasitic capacitance of the conventional embedded inductor becomes a major target in designing the embedded inductor.